Up to now, there is an SiC semiconductor device having a trench gate structure as a structure in which a channel density is increased to allow a large current to flow. In such a SiC semiconductor device having the trench gate structure, there is a possibility that a breakdown electric field strength of SiC is high, and a dielectric breakdown may occur by applying a high electric field to a bottom portion of a trench. For that reason, electric field relaxation layers of a single layer structure are formed below a base layer between opposing trench gates to relax an electric field, to thereby prevent a dielectric breakdown.
However, although the electric field relaxation effect to the trench gate portion is obtained with the provision of the electric field relaxation layer having the single layer structure, a depletion layer extends between the adjacent electric field relaxation layers to generate a JFET resistance region, resulting in such a problem that an on-resistance increases.
On the other hand, a MOSFET having a structure in which the electric field relaxation layers extend from a substrate surface to a deeper portion than the trench gate, lateral regions in which a width of the electric field relaxation layers is expanded in a lateral direction in the bottom portion are provided, and the lateral regions are arranged below the trench gate. With the above structure, since a carrier density in the drift layer can be lowered within a range sandwiched between the respective lateral regions, an electric field intensity distribution can be suppressed at a position deeper than the bottom portion of the trench and a withstand voltage characteristic can be improved. Furthermore, since an interval between the lateral regions is determined according to only formation positions of the lateral regions, the interval between the lateral regions can be prevented from being affected by a positional deviation caused by a manufacturing error of the trench gate and the electric field relaxation layers.
In the case of such a structure, the electric field relaxation layers extending from the surface of the substrate to the portion deeper than the trench gate are configured at the same concentration. However, because the electric field relaxation effects are not obtained if the electric field relaxation layers are formed at a low concentration, the electric field relaxation layers are formed at a high concentration. However, when the electric field relaxation layers are configured at the high concentration, the depletion layer from the electric field relaxation layers tends to extend in the vicinity of the trench, as a result of which a JFET resistance region is generated, which causes a problem that the on-resistance increases.
Under the circumstance, the SiC semiconductor device disclosed in Patent Literature 1 have been proposed as a measure for solving the problems occurring in the above respective structures. Specifically, the SiC semiconductor device is of a structure in which while the electric field relaxation layers are formed so as to intersect with the trench gate having one direction as a longitudinal direction, the electric field relaxation layers are configured as a two-layer structure having different impurity concentrations in a depth direction where a deep portion is a high concentration region and a shallow portion is a low concentration region. With the above structure, the SiC semiconductor device obtains both of the effect of relaxing the electric field in the bottom portion of the trench in the deep layer set as the high concentration region, and the effect of restraining the depletion layer from extending in the vicinity of the trench in the shallow layer set as the low concentration region to reduce a JFET resistance. In addition, the SiC semiconductor device makes it possible to be less likely to generate a manufacturing error caused by a deviation in the position of the electric field relaxation layer and the trench.
However, in the structure of Patent Literature 1, although the electric field relaxation effect, the JFET resistance reduction effect, and the effect of increasing a manufacturing error tolerance can be obtained, because a trench gate is formed on a damage in a crystal structure generated at the time of forming the electric field relaxation layers, the reliability of the trench gate is reduced. That is, after the electric field relaxation layers have been formed by ion implantation, the base region or the like is epitaxially grown on the electric field relaxation layers and then intersects with the electric field relaxation layers. For that reason, because crystal defects at the time of ion implantation are also taken over by a layer formed on the crystal defects, and the trench gate is formed so as to intersect with a portion where the crystal defects are inherited, variations may occur in the quality of the gate insulating film, or a leak path may be formed. For that reason, such a problem that the reliability of the trench gate is lowered occurs.